1. Field of the Invention
The present invention relates to a printed circuit board, in particular, to a printed circuit board for package on package and a manufacturing method thereof in which there is a level difference in the surface of the substrate for mounting 2 or more IC chips on the bottom substrate of the printed circuit board.
2. Description of the Related Art
Semiconductor packaging provides electrical connection to semiconductor chips including circuits and is seal-packaged to protect from any external impact so that it allows effect on the physical function and appearance for useful in the real life.
The semiconductor package is an outcome of the semiconductor packaging process to manufacture semiconductor chips as a product.
Even though from several tens to several hundreds of chips printed with identical circuits can be placed on one wafer, semiconductor chip itself cannot transfer or receive an electrical signal with electricity supplied from outside.
Moreover, the semiconductor chip can be damaged easily by an external impact because the semiconductor chip has fine circuits. That is, the semiconductor chip itself cannot be a perfect product, but it may play a role as a perfect product by mounting it on a printed circuit board.
A packaging technology affects reduction of the size of the semiconductor chip, improvement of ability to emit heat, electrical performance, reliability and depreciation. Therefore improvement of packaging technology is required to support high integration and high efficiency of semiconductor devices. The semiconductor package not only satisfies requirements of the semiconductor devices but also has packaging performance suitable for the condition when the chips are mounted on a printed circuit board.
Space to mount semiconductor chips currently has become smaller with high demand of miniaturized portable electronic devices and the number of semiconductor chips has currently been increased with high demand of multi-functions and high performance of products.
Because of the miniaturization, more capacity, and high processing speed of semiconductor chips, with rapid development of multimedia and computer communication industries, researches to find thinner semiconductor packages and higher integration with more pins have been increased.
Therefore, the semiconductor package must follow the trend of lightness, thinness and smallness in order to raise the efficiency of packaging per unit volume. According to the above trend, a chip size package (CSP), of which the size is almost same as the size of a chip, has introduced.
Beyond the package, which is minimized to the size of a chip, a stacked CSP (SCSP), which stacks one chip on another chip, or a multi chip module (MCM) package, which arranges several semiconductor chips having different functions in one package, has been also developed.
Package on package (POP), which stacks one package on another package, becomes popular for high density package. A thickness of a whole package is the most restriction for the embodiment of POP. There is a demand for mounting 2 or more semiconductor chips, instead of one semiconductor chip, on the bottom substrate, so that the performance of POP becomes higher.
FIGS. 1a and 1b show the figures of the structure of POP according to a conventional technology and a recent tendency.
Referring to FIG. 1a, conventionally one semiconductor chip 100 is stacked on a bottom substrate 10, and a thickness of a whole package is H1.
Referring to FIG. 1b, according to a recent tendency, two semiconductor chips 100 and 110 are stacked on a bottom substrate 10. In this case, a thickness of a whole package is H2. H2 is larger than H1 shown in FIG. 1a, which is against the tendency of lightness, thinness and smallness
The thickness problem has been tried to solve by using a die thinning technology in order to lower the thickness of a whole package according to the tendency of lightness, thinness and smallness. But there are problems of function errors caused by operating semiconductor chips for a long period of time when thin semiconductor chips are used.